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[VHDL-FPGA-Verilog] FIFO_Design

Description: 一种基于格雷码的异步FIFO设计与实现,8*8位的fifo VHDL 源码-Gray-code based on the Asynchronous FIFO Design and Implementation
Platform: | Size: 90112 | Author: qwe | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: FIFO，vhdl实现，希望可以有帮助,大家加油-FIFO VHDL
Platform: | Size: 1024 | Author: Carlin | Hits:

[VHDL-FPGA-Verilog] fifotop

Description: 基于FPGA编写的VHDL语言，FIFO代码程序。 程序完整。-VHDL-based FPGA written language, FIFO procedure code. Complete the procedure.
Platform: | Size: 2100224 | Author: 李芳 | Hits:

[Software Engineering] CummingsSNUG2002SJ_FIFO2

Description: Simulation and Synthesis Techniques for Asynchronous FIFO Design with Asynchronous Pointer Comparisons
Platform: | Size: 101376 | Author: sumit | Hits:

[Video Capture] camera_up

Description: Camera Interface模块是视频输入转换存储模块。该模块一端接通用的video camera设备，另一端接AHB总线。实现了将Camera捕捉到的数据进行转换、并通过DMA存储到memory中。该IP支持ITU-R BT 601/656 8-bit 模式。支持YCbCr, RGB格式输入。可以将camera产生的YCbCr信号转换成24bit RGB 信号，然后下采样生成16bit RGB 5：6：5的LCD能直接读取显示的数据。该设备支持图像的镜像和翻转，以便适应手持式设备在移动环境中图像的捕捉。可变的同步信号极性使得可以兼容各种摄像头外设。Camera Interface兼容AMBA规范， AHB SLAVE接口，用于读取软件配置数据和设置数据存放地址和1帧数据占用的空间。-The Camera IP Core is small and flexible video data coverter. It is connected to a typical video camera ICs with 8-bit digital video data, Horizontal synchronization and Vertical synchronization signals. The core is connected through FIFO to a WISHBONE bus on the other side. Both sides of the core can operate at fully asynchronous clock frequencies. The Camera IP Core convertes 4:2:2 YCbCr video data (sometimes called YUV, but not totally the same Y is the same, while Cb and Cr are U and V multiplied by a constant) to a 24-bit RGB. 24-bit or 16-bit RGB data, downsampled from 24-bit RGB, is then sent to the system (video) memory, however conversion can also be by-passed. Interrupt can be generated after frame-buffer in system (video) memory is filled up or after setable number of horizontal lines written to frame-buffer.
Platform: | Size: 32768 | Author: 孙喆 | Hits:

[VHDL-FPGA-Verilog] gencontrol

Description: 高速任意波形产生器控制模块 控制NCO,FIFO，并串转换-hign-speed wfgenerator control
Platform: | Size: 1024 | Author: ted yang | Hits:

[OS Develop] UART

Description: A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.-A badic controller for the UART. It incorporates a -- transmit and receive FIFO (from Max+Plus II s MegaWizard -- plug-in manager). Note that no checking is done to see -- whether the FIFOs are overflowing or not. This strictly -- handles the transmitting and receiving of the data.
Platform: | Size: 2048 | Author: Viral | Hits:

[VHDL-FPGA-Verilog] ASYNCFIFO

Description: 异步FIFO的FPGA实现,XILINX FPGA, ISE ,VHDL语言实现-asynchronous fifo
Platform: | Size: 75776 | Author: Denny | Hits:

[VHDL-FPGA-Verilog] VHDL06

Description: 16×4bit的FIFO设计代码，学习代码，请在下载24小时后删除。-16 × 4bit the FIFO design code, learning the code, please delete after 24 hours to download.
Platform: | Size: 1024 | Author: yanyinhong | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: VHDL code for first in first out register
Platform: | Size: 1024 | Author: Davood | Hits:

[OS Develop] FIFOexperience

Description: 华为内部关于FIFO的经验之谈，深入了解FIFO-Huawei on the FIFO' s internal experiences
Platform: | Size: 516096 | Author: 王辉 | Hits:

[VHDL-FPGA-Verilog] 8fifo

Description: 可综合的 8x8 fifo VHDL 源代码-Can be integrated 8x8 fifo VHDL source code
Platform: | Size: 3072 | Author: qaz | Hits:

[VHDL-FPGA-Verilog] fifi

Description: FIFO code written in VHDL
Platform: | Size: 11264 | Author: Harini | Hits:

[VHDL-FPGA-Verilog] THS1206

Description: FPGA来实现数据采集，AD采用TI公司的THS1206，高速并行AD，内含16字FIFO，降低硬件复杂度。-FPGA to realize data acquisition, AD using TI company s THS1206, high-speed parallel AD, containing the 16-character FIFO, to reduce hardware complexity.
Platform: | Size: 1024 | Author: LX | Hits:

[VHDL-FPGA-Verilog] fifo

Description: first in first out VHDL code
Platform: | Size: 1024 | Author: LXG | Hits:

[VHDL-FPGA-Verilog] caiyang

Description: 种用FPGA 实现对高速A/ D 转换芯片的控制电路,系统以MAX125 为例,详细介绍了含有FIFO 存储器的A/ D 采样控制电路的设计方法,并给出了A/D 采样控制电路的V HDL 源程序和整个采样存储的顶层电路原理图.-Species with FPGA to achieve high-speed A/D conversion chip control circuit, the system as an example to MAX125 details FIFO memory contains A/D sampling control circuit design method, and gives the A/D sampling control circuit of the V HDL source code and the sample stored in the top-level circuit schematic.
Platform: | Size: 338944 | Author: 于银 | Hits:

[Other] FIFORAM

Description: FIFO RAM 存储器以FIFO形式进行的读取-FIFO RAM
Platform: | Size: 331776 | Author: SMILE | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 一个先入先出FIFO的VHDL实现，程序经过了编译验证。-A FIFO FIFO to achieve the VHDL, verification procedures have been compiled.
Platform: | Size: 456704 | Author: Robert Shen | Hits:

[VHDL-FPGA-Verilog] yuyincaiji

Description: 语音采集与回放系统源代码：1.为了使读音数据存储的时间更长，速度更快，选用了256K*16Bit的SRAM；2.为了减少单片机的控制复杂度，使用了FPGA来控制SRAM的读写操作，节约了不少单片机的I/O资源；3.为了以后的高速数据存储，本设计中加入了fifo,其位宽及深度可在程序中自由设置，方便灵活。-Speech acquisition and playback system source code: 1. In order to make pronunciation longer data storage, faster, 256K* 16Bit selected the SRAM 2. In order to reduce the complexity of single-chip control, the use of the FPGA to control the SRAM The read and write operations, saving a lot of microcontroller I/O resources 3. to future high-speed data storage, the design into the fifo, its width and depth can be set up in the process of free, convenient and flexible.
Platform: | Size: 804864 | Author: song | Hits:

[VHDL-FPGA-Verilog] Asynchronous_FIFO_v6_1

Description: 详细介绍了异步FIFO的设计方法,以及fpga的仿真波形-Described in detail the design of asynchronous FIFO method and the simulation waveform fpga
Platform: | Size: 133120 | Author: wushaojie | Hits:
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